LEI'S DESIGN SERVICES

EXPERIENCED IN CHIP DESIGN VERIFICATION

UVM ETHERNET RANDOM TESTBENCH DIAGRAM

The UVM ethernet random testbench diagram below has four hierarchies based on UVM methodology.  The top level testbench, gmii_tb_top, instantiates gmii_test, gmii_if, and gmii_ethernet_top.  gmii_test is the UVM top level.  gmii_if is the virtual interface that connects the signals of the DUT and the UVM top level together.  gmii_ethernet_top is the DUT. 

The UVM top level, gmii_test, encapsulates gmii_env where gmii_test is the UVM test.  gmii_env encapsulates gmii_agent and gmii_scoreboard where gmii_env is the UVM environment.  gmii_agent encapsulates gmii_driver and gmii_sequencer where gmii_agent is the UVM agent.  gmii_driver and gmii_sequencer are connected using TLM where random packet transactions are driven to the DUT via the virtual interface, gmii_if.  gmii_scoreboard does calculations and comparisons based on the DUT inputs driven by the gmii_driver and DUT outputs from the gmii_monitor.  The UVM testbench runs and detects errors on the fly.

 

UVM GMII ETHERNET TESTBENCH WAVEFORM

GMII ETHERNET DATA FRAME PACKET FORMAT DIAGRAM

UVM GMII ETHERNET DATA FRAME PACKET WAVEFORM EXAMPLE

GMII PAUSE FRAME FORMAT DIAGRAM

UVM GMII ETHERNET PAUSE FRAME PACKET WAVEFORM EXAMPLE

GMII ETHERNET PRIORITY FLOW CONTROL FRAME PACKET FORMAT DIAGRAM

UVM GMII ETHERNET PRIORITY FLOW CONTROL FRAME PACKET WAVEFORM

GMII ETHERNET VLAN TAG FRAME PACKET FORMAT DIAGRAM

UVM GMII ETHERNET VLAN TAG FRAME PACKET WAVEFORM EXAMPLE